The present invention relates to a simulator and a simulation method for verifying a function or a behavior of a logic circuit.
Recently, in order to efficiently develop large-scale and complicated LSIs, the function/behavior of the LSIs are described by using a hardware description language such as VHDL and Verilog HDL or a function diagram expressed by charts and characters in designing the LSIs. Examples of widely used design methods include a simulation method in which a functional simulation or a logical simulation is carried out by using a program described by using a hardware description language or a function diagram, and a top-down design method using a logic synthesizing tool.
In a conventional simulator used in the top-down design method, however, the function/behavior of a logic circuit is processed in a simulation part with a register transfer level or the like used as one processing unit.
Specifically, when an event-driven system is adopted for the simulation, the simulator repeats the following series of processings: An updating processing of a state value of a register executed with an event registered in an event list; an event transmission processing for stacking an evaluation unit for evaluating a data transfer of a referred register on an evaluation stack; an evaluation processing for evaluating the evaluation unit stacked on the evaluation stack; and an event registration processing for registering an event in the event list when the event is newly generated from the data transfer evaluated in the evaluation processing.
Alternatively, when a cycle-based system is adopted for the simulation, the simulator carries out the following series of processings: An evaluation processing for evaluating an evaluation unit for evaluating a data transfer of a register in each clock cycle, for example, at each rise of a clock signal; and a state value updating processing for updating a state value of the register.
Such a conventional simulator has, however, the following two problems:
(1) Both the event-driven system and the cycle-based system require a longer processing time for the simulation as the number of data transfers in the logic circuit is larger. In particular, in simulating a circuit including a large number of registers such as a data path type circuit, the number of the data transfers to the respective registers is large because the number of the registers is large, and hence, the number of evaluation units is also large. As a result, a very long simulation time is required for such a circuit. PA1 (2) In simulating a circuit including a multi-cycle path operated in accordance with plural clock cycles, the multi-cycle path is also evaluated as one clock cycle when the simulation is carried out by using a 0-delay model where a delay time is not considered. Therefore, the behavior of the multi-cycle path cannot be correctly simulated.